Design of residue generators and multioperand modular adders using carry-save adders

Residue generator is an essential building block of encoding/decoding circuitry for arithmetic error detecting codes and binary-to-residue number system (RNS) converter. In either case, a residue generator is an overhead for a system and as such it should be built with minimum amount of hardware and should not compromise the speed of a system. Multioperand modular adder (MOMA) is a computational element used to implement various operations in digital signal processing systems using RNS. In this paper, a comprehensive study of new residue generators and MOMA's is presented. The design methods given here take advantage of the periodicity of the series of powers of 2 taken modulo A (A is a module). Four design schemes of the n-input residue generators mod A, which are best suited for various pairs of R. and A, are proposed. Their pipelined versions can be clocked with the cycle determined by the delay of a full-adder and a latch. A family of design methods for parallel and word-serial, using similar concepts, is also given. Both classes of circuits employ new highly-parallel schemes using carry-save adders with endaround carry and a minimal amount of ROM and are well-suited for VLSI implementation. They are faster and use less hardware than similar circuits known to date. One of the MOMA's can be used to build a high-speed residue-to-binary converter based on the Chinese remainder theorem.